This invention relates to signal detect circuitry for a high-speed serial interface, particularly in a programmable device.
Many integrated circuit devices can be programmed. Examples of programmable integrated circuit devices include volatile and non-volatile memory devices, field programmable gate arrays (“FPGAs”), programmable logic devices (“PLDs”) and complex programmable logic devices (“CPLDs”). Other examples of programmable integrated circuit devices include application-specific integrated circuits (ASICs), processors and microcontrollers that are programmable via internal or external memory. Programmable integrated circuit devices, such as programmable logic devices (PLDs) in particular, frequently incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards. Typically, a PLD may have multiple high-speed serial interface channels.
PLDs frequently incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards—e.g., the XAUI (10 Gbps Extended Attachment Unit Interface) standard. In accordance with the XAUI standard, a high-speed serial interface includes transceiver groups known as “quads,” each of which includes four transceivers and some central logic.
Each transceiver typically includes signal detection circuitry in both its receiver and transceiver portions. In the receiver portion, the signal detection circuitry typically is referred to as “signal detect” or “SD,” and generates a signal that alerts the rest of the receiver to incoming data. In the transmitter portion, the signal detection circuitry typically is referred to as “receiver detect” or “R×D,” and generates a signal when it detects that transmitted signals are being received by a receiver at the other end. The same is true in serial transceivers other than those used with the XAUI standard.
Signal detection at high speeds is difficult. This is recognized in the field, to the point that the PCI-Express Generation 2 (PCIe2) high-speed serial standard specifies a data pattern to allow easier detection of the presence of a signal.
Many known signal detection circuits are analog, and typically incorporate a rectifier and an integrator, which produce a signal that is then compared to a reference level. However, the nature of rectification and integration is such that they cause a loss of accuracy. Specifically, this technique typically utilizes a high-speed peak detector in a voltage-follower configuration. The voltage follower is designed so that the charge current is much higher than the discharge current. This may lead to static offset. In addition, the required sense amplifier needs to have an extremely large bandwidth, making it very difficult to design. Moreover, mismatches and pattern dependencies can cause the actual detection level to vary dramatically from unit to unit.
Timing issues may also arise because many high-speed serial protocols are asynchronous. If input data are sampled in accordance with the system clock, and the sampling time happens to fall within a transition between data eyes, then even if data were present, it might not be detected.